Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Loop

A sequential statement used to execute a set of sequential statements repeatedly.

Syntax

  [LoopLabel:] loop
    SequentialStatements...
  end loop [LoopLabel];
    

Where

See Sequential Statement

Things to remember

A loop is an infinite loop (and thus an error) unless it contains an exit or wait statement.

Synthesis

Not generally synthesizable. Some tools do allow loops containing wait statements to describe implicit finite state machines, but this is not recommended practice.

Example

  loop
    wait until Clock = '1';
    exit when Reset = '1';
    Div2 <= not Div2;
  end loop;
    

See Also

For Loop, While Loop, Exit, Next